ALDEC ACTIVE HDL 6.2SP1

Creation Time	Jan. 6, 2024, 4:08 a.m.
Last Access Time	April 21, 2025, 9:30 a.m.
File Size	469.9 MB
Keywords	ACTIVE 2SP1 HDL ALDEC 6
Total Requests	38
Total Files	422
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data1.cab 145.6 MB
Service_Pack_1_SPK.exe 62.2 MB
SCH/Xilinx/data1.cab 55.9 MB
vhdl/ChipExpress/data1.cab 34.9 MB
vhdl/Actel/data1.cab 25.6 MB
vhdl/Xilinx/data1.cab 18.7 MB
vhdl/LatticeCPLD/data1.cab 16.7 MB
VERILOG/Xilinx/data1.cab 14.0 MB
vhdl/Altera/data1.cab 13.1 MB
vhdl/LatticeORCA/data1.cab 10.2 MB
VERILOG/Actel/data1.cab 8.4 MB
VERILOG/LatticeCPLD/data1.cab 7.3 MB
VERILOG/ChipExpress/data1.cab 6.2 MB
VERILOG/Altera/data1.cab 6.1 MB
jc/FarmMC.exe 5.3 MB
vhdl/Atmel/data1.cab 4.3 MB
VERILOG/LatticeORCA/data1.cab 4.1 MB
VERILOG/QuickL/data1.cab 2.3 MB
vhdl/QuickL/data1.cab 2.1 MB
VERILOG/Atmel/data1.cab 2.0 MB
vhdl/Triscend/data1.cab 1.7 MB
vhdl/Cypress/data1.cab 1.2 MB
VERILOG/Cypress/data1.cab 954.8 KB
VERILOG/Triscend/data1.cab 905.0 KB
SCH/Xilinx/data1.hdr 488.8 KB
data1.hdr 462.1 KB
SCH/Xilinx/_INST32I.EX_ 289.7 KB
VERILOG/Actel/_INST32I.EX_ 289.7 KB
VERILOG/Altera/_INST32I.EX_ 289.7 KB
VERILOG/Atmel/_INST32I.EX_ 289.7 KB
VERILOG/ChipExpress/_INST32I.EX_ 289.7 KB
VERILOG/Cypress/_INST32I.EX_ 289.7 KB
VERILOG/LatticeCPLD/_INST32I.EX_ 289.7 KB
VERILOG/LatticeORCA/_INST32I.EX_ 289.7 KB
VERILOG/QuickL/_INST32I.EX_ 289.7 KB
VERILOG/Triscend/_INST32I.EX_ 289.7 KB
VERILOG/Xilinx/_INST32I.EX_ 289.7 KB
vhdl/Actel/_INST32I.EX_ 289.7 KB
vhdl/Altera/_INST32I.EX_ 289.7 KB
vhdl/Atmel/_INST32I.EX_ 289.7 KB
vhdl/ChipExpress/_INST32I.EX_ 289.7 KB
vhdl/Cypress/_INST32I.EX_ 289.7 KB
vhdl/LatticeCPLD/_INST32I.EX_ 289.7 KB
vhdl/LatticeORCA/_INST32I.EX_ 289.7 KB
vhdl/QuickL/_INST32I.EX_ 289.7 KB
vhdl/Triscend/_INST32I.EX_ 289.7 KB
vhdl/Xilinx/_INST32I.EX_ 289.7 KB
setup.ins 223.8 KB
SCH/Xilinx/_sys1.cab 171.4 KB
VERILOG/Actel/_sys1.cab 171.4 KB
VERILOG/Altera/_sys1.cab 171.4 KB
VERILOG/Atmel/_sys1.cab 171.4 KB
VERILOG/ChipExpress/_sys1.cab 171.4 KB
VERILOG/Cypress/_sys1.cab 171.4 KB
VERILOG/LatticeCPLD/_sys1.cab 171.4 KB
VERILOG/LatticeORCA/_sys1.cab 171.4 KB
VERILOG/QuickL/_sys1.cab 171.4 KB
VERILOG/Triscend/_sys1.cab 171.4 KB
VERILOG/Xilinx/_sys1.cab 171.4 KB
vhdl/Actel/_sys1.cab 171.4 KB
vhdl/Altera/_sys1.cab 171.4 KB
vhdl/Atmel/_sys1.cab 171.4 KB
vhdl/ChipExpress/_sys1.cab 171.4 KB
vhdl/Cypress/_sys1.cab 171.4 KB
vhdl/LatticeCPLD/_sys1.cab 171.4 KB
vhdl/LatticeORCA/_sys1.cab 171.4 KB
vhdl/QuickL/_sys1.cab 171.4 KB
vhdl/Triscend/_sys1.cab 171.4 KB
vhdl/Xilinx/_sys1.cab 171.4 KB
Relnotes1.htm 161.0 KB
crack/RORAHDL62SP1.exe 144.8 KB
VERILOG/Xilinx/data1.hdr 144.7 KB
VERILOG/LatticeORCA/data1.hdr 131.1 KB
Relnotes.htm 117.4 KB
Appendix.htm 115.5 KB
SCH/Xilinx/Setup.exe 72.0 KB
VERILOG/Actel/Setup.exe 72.0 KB
VERILOG/Altera/Setup.exe 72.0 KB
VERILOG/Atmel/Setup.exe 72.0 KB
VERILOG/ChipExpress/Setup.exe 72.0 KB
VERILOG/Cypress/Setup.exe 72.0 KB
VERILOG/LatticeCPLD/Setup.exe 72.0 KB
VERILOG/LatticeORCA/Setup.exe 72.0 KB
VERILOG/QuickL/Setup.exe 72.0 KB
VERILOG/Triscend/Setup.exe 72.0 KB
VERILOG/Xilinx/Setup.exe 72.0 KB
vhdl/Actel/Setup.exe 72.0 KB
vhdl/Altera/Setup.exe 72.0 KB
vhdl/Atmel/Setup.exe 72.0 KB
vhdl/ChipExpress/Setup.exe 72.0 KB
vhdl/Cypress/Setup.exe 72.0 KB
vhdl/LatticeCPLD/Setup.exe 72.0 KB
vhdl/LatticeORCA/Setup.exe 72.0 KB
vhdl/QuickL/Setup.exe 72.0 KB
vhdl/Triscend/Setup.exe 72.0 KB
vhdl/Xilinx/Setup.exe 72.0 KB
Setup.exe 72.0 KB
VERILOG/ChipExpress/setup.ins 71.5 KB
VERILOG/LatticeCPLD/setup.ins 71.5 KB
VERILOG/LatticeORCA/setup.ins 71.5 KB
VERILOG/QuickL/setup.ins 71.5 KB
vhdl/ChipExpress/setup.ins 71.5 KB
vhdl/LatticeCPLD/setup.ins 71.5 KB
vhdl/LatticeORCA/setup.ins 71.5 KB
SCH/Xilinx/setup.ins 71.5 KB
VERILOG/Triscend/setup.ins 71.5 KB
VERILOG/Cypress/setup.ins 71.5 KB
vhdl/QuickL/setup.ins 71.5 KB
VERILOG/Altera/setup.ins 71.5 KB
VERILOG/Xilinx/setup.ins 71.5 KB
VERILOG/Actel/setup.ins 71.5 KB
VERILOG/Atmel/setup.ins 71.5 KB
vhdl/Triscend/setup.ins 71.5 KB
vhdl/Cypress/setup.ins 71.5 KB
vhdl/Altera/setup.ins 71.5 KB
vhdl/Xilinx/setup.ins 71.5 KB
vhdl/Actel/setup.ins 71.5 KB
vhdl/Atmel/setup.ins 71.5 KB
VERILOG/Atmel/data1.hdr 61.3 KB
Rel00009.gif 57.3 KB
crack/crack1.exe 52.4 KB
crack1.exe 52.4 KB
vhdl/Xilinx/data1.hdr 45.2 KB
Relnotoc.htm 39.8 KB
SCH/Xilinx/_Setup.dll 34.0 KB
VERILOG/Actel/_Setup.dll 34.0 KB
VERILOG/Altera/_Setup.dll 34.0 KB
VERILOG/Atmel/_Setup.dll 34.0 KB
VERILOG/ChipExpress/_Setup.dll 34.0 KB
VERILOG/Cypress/_Setup.dll 34.0 KB
VERILOG/LatticeCPLD/_Setup.dll 34.0 KB
VERILOG/LatticeORCA/_Setup.dll 34.0 KB
VERILOG/QuickL/_Setup.dll 34.0 KB
VERILOG/Triscend/_Setup.dll 34.0 KB
VERILOG/Xilinx/_Setup.dll 34.0 KB
vhdl/Actel/_Setup.dll 34.0 KB
vhdl/Altera/_Setup.dll 34.0 KB
vhdl/Atmel/_Setup.dll 34.0 KB
vhdl/ChipExpress/_Setup.dll 34.0 KB
vhdl/Cypress/_Setup.dll 34.0 KB
vhdl/LatticeCPLD/_Setup.dll 34.0 KB
vhdl/LatticeORCA/_Setup.dll 34.0 KB
vhdl/QuickL/_Setup.dll 34.0 KB
vhdl/Triscend/_Setup.dll 34.0 KB
vhdl/Xilinx/_Setup.dll 34.0 KB
VERILOG/LatticeCPLD/data1.hdr 29.6 KB
SCH/Xilinx/_ISDel.exe 27.0 KB
VERILOG/Actel/_ISDel.exe 27.0 KB
VERILOG/Altera/_ISDel.exe 27.0 KB
VERILOG/Atmel/_ISDel.exe 27.0 KB
VERILOG/ChipExpress/_ISDel.exe 27.0 KB
VERILOG/Cypress/_ISDel.exe 27.0 KB
VERILOG/LatticeCPLD/_ISDel.exe 27.0 KB
VERILOG/LatticeORCA/_ISDel.exe 27.0 KB
VERILOG/QuickL/_ISDel.exe 27.0 KB
VERILOG/Triscend/_ISDel.exe 27.0 KB
VERILOG/Xilinx/_ISDel.exe 27.0 KB
vhdl/Actel/_ISDel.exe 27.0 KB
vhdl/Altera/_ISDel.exe 27.0 KB
vhdl/Atmel/_ISDel.exe 27.0 KB
vhdl/ChipExpress/_ISDel.exe 27.0 KB
vhdl/Cypress/_ISDel.exe 27.0 KB
vhdl/LatticeCPLD/_ISDel.exe 27.0 KB
vhdl/LatticeORCA/_ISDel.exe 27.0 KB
vhdl/QuickL/_ISDel.exe 27.0 KB
vhdl/Triscend/_ISDel.exe 27.0 KB
vhdl/Xilinx/_ISDel.exe 27.0 KB
vhdl/Altera/data1.hdr 24.6 KB
SCH/Xilinx/lang.dat 23.0 KB
VERILOG/Actel/lang.dat 23.0 KB
VERILOG/Altera/lang.dat 23.0 KB
VERILOG/Atmel/lang.dat 23.0 KB
VERILOG/ChipExpress/lang.dat 23.0 KB
VERILOG/Cypress/lang.dat 23.0 KB
VERILOG/LatticeCPLD/lang.dat 23.0 KB
VERILOG/LatticeORCA/lang.dat 23.0 KB
VERILOG/QuickL/lang.dat 23.0 KB
VERILOG/Triscend/lang.dat 23.0 KB
VERILOG/Xilinx/lang.dat 23.0 KB
vhdl/Actel/lang.dat 23.0 KB
vhdl/Altera/lang.dat 23.0 KB
vhdl/Atmel/lang.dat 23.0 KB
vhdl/ChipExpress/lang.dat 23.0 KB
vhdl/Cypress/lang.dat 23.0 KB
vhdl/LatticeCPLD/lang.dat 23.0 KB
vhdl/LatticeORCA/lang.dat 23.0 KB
vhdl/QuickL/lang.dat 23.0 KB
vhdl/Triscend/lang.dat 23.0 KB
vhdl/Xilinx/lang.dat 23.0 KB
lang.dat 23.0 KB
VERILOG/Altera/data1.hdr 21.8 KB
vhdl/ChipExpress/data1.hdr 20.8 KB
vhdl/LatticeCPLD/data1.hdr 20.6 KB
VERILOG/Actel/data1.hdr 19.3 KB
SCH/Xilinx/_user1.cab 18.4 KB
VERILOG/Actel/_user1.cab 18.4 KB
VERILOG/Altera/_user1.cab 18.4 KB
VERILOG/Atmel/_user1.cab 18.4 KB
VERILOG/ChipExpress/_user1.cab 18.4 KB
VERILOG/Cypress/_user1.cab 18.4 KB
VERILOG/LatticeCPLD/_user1.cab 18.4 KB
VERILOG/LatticeORCA/_user1.cab 18.4 KB
VERILOG/QuickL/_user1.cab 18.4 KB
VERILOG/Triscend/_user1.cab 18.4 KB
VERILOG/Xilinx/_user1.cab 18.4 KB
vhdl/Actel/_user1.cab 18.4 KB
vhdl/Altera/_user1.cab 18.4 KB
vhdl/Atmel/_user1.cab 18.4 KB
vhdl/ChipExpress/_user1.cab 18.4 KB
vhdl/Cypress/_user1.cab 18.4 KB
vhdl/LatticeCPLD/_user1.cab 18.4 KB
vhdl/LatticeORCA/_user1.cab 18.4 KB
vhdl/QuickL/_user1.cab 18.4 KB
vhdl/Triscend/_user1.cab 18.4 KB
vhdl/Xilinx/_user1.cab 18.4 KB
vhdl/Actel/data1.hdr 17.0 KB
rel00035.gif 14.8 KB
vhdl/LatticeORCA/data1.hdr 12.0 KB
aldec_bg.gif 10.1 KB
VERILOG/ChipExpress/data1.hdr 9.8 KB
Image1.gif 9.5 KB
vhdl/Atmel/data1.hdr 9.4 KB
image6.gif 9.3 KB
crack/license.dat 8.8 KB
image7.gif 8.6 KB
image8.gif 8.6 KB
image3.gif 8.4 KB
Relnotes.css 8.1 KB
image4.gif 7.7 KB
Rel00008.gif 6.9 KB
Image2.gif 6.7 KB
VERILOG/QuickL/data1.hdr 6.6 KB
vhdl/QuickL/data1.hdr 6.2 KB
vhdl/Cypress/data1.hdr 5.8 KB
image5.gif 5.8 KB
VERILOG/Cypress/data1.hdr 5.4 KB
Rel00007.gif 5.0 KB
legends.nfo 5.0 KB
VERILOG/Triscend/data1.hdr 4.5 KB
vhdl/Triscend/data1.hdr 4.4 KB
SCH/Xilinx/_user1.hdr 4.3 KB
VERILOG/Actel/_user1.hdr 4.3 KB
VERILOG/Altera/_user1.hdr 4.3 KB
VERILOG/Atmel/_user1.hdr 4.3 KB
VERILOG/ChipExpress/_user1.hdr 4.3 KB
VERILOG/Cypress/_user1.hdr 4.3 KB
VERILOG/LatticeCPLD/_user1.hdr 4.3 KB
VERILOG/LatticeORCA/_user1.hdr 4.3 KB
VERILOG/QuickL/_user1.hdr 4.3 KB
VERILOG/Triscend/_user1.hdr 4.3 KB
VERILOG/Xilinx/_user1.hdr 4.3 KB
vhdl/Actel/_user1.hdr 4.3 KB
vhdl/Altera/_user1.hdr 4.3 KB
vhdl/Atmel/_user1.hdr 4.3 KB
vhdl/ChipExpress/_user1.hdr 4.3 KB
vhdl/Cypress/_user1.hdr 4.3 KB
vhdl/LatticeCPLD/_user1.hdr 4.3 KB
vhdl/LatticeORCA/_user1.hdr 4.3 KB
vhdl/QuickL/_user1.hdr 4.3 KB
vhdl/Triscend/_user1.hdr 4.3 KB
vhdl/Xilinx/_user1.hdr 4.3 KB
SCH/Xilinx/_sys1.hdr 3.8 KB
VERILOG/Actel/_sys1.hdr 3.8 KB
VERILOG/Altera/_sys1.hdr 3.8 KB
VERILOG/Atmel/_sys1.hdr 3.8 KB
VERILOG/ChipExpress/_sys1.hdr 3.8 KB
VERILOG/Cypress/_sys1.hdr 3.8 KB
VERILOG/LatticeCPLD/_sys1.hdr 3.8 KB
VERILOG/LatticeORCA/_sys1.hdr 3.8 KB
VERILOG/QuickL/_sys1.hdr 3.8 KB
VERILOG/Triscend/_sys1.hdr 3.8 KB
VERILOG/Xilinx/_sys1.hdr 3.8 KB
vhdl/Actel/_sys1.hdr 3.8 KB
vhdl/Altera/_sys1.hdr 3.8 KB
vhdl/Atmel/_sys1.hdr 3.8 KB
vhdl/ChipExpress/_sys1.hdr 3.8 KB
vhdl/Cypress/_sys1.hdr 3.8 KB
vhdl/LatticeCPLD/_sys1.hdr 3.8 KB
vhdl/LatticeORCA/_sys1.hdr 3.8 KB
vhdl/QuickL/_sys1.hdr 3.8 KB
vhdl/Triscend/_sys1.hdr 3.8 KB
vhdl/Xilinx/_sys1.hdr 3.8 KB
licupdnfo.html 2.3 KB
ReadMe_rus.txt 1.2 KB
layout.bin 1.0 KB
crack/readme.nfo 703 bytes
license.html 638 bytes
SCH/Xilinx/layout.bin 609 bytes
VERILOG/Actel/layout.bin 609 bytes
VERILOG/Altera/layout.bin 609 bytes
VERILOG/Atmel/layout.bin 609 bytes
VERILOG/ChipExpress/layout.bin 609 bytes
VERILOG/Cypress/layout.bin 609 bytes
VERILOG/LatticeCPLD/layout.bin 609 bytes
VERILOG/LatticeORCA/layout.bin 609 bytes
VERILOG/QuickL/layout.bin 609 bytes
VERILOG/Triscend/layout.bin 609 bytes
VERILOG/Xilinx/layout.bin 609 bytes
vhdl/Actel/layout.bin 609 bytes
vhdl/Altera/layout.bin 609 bytes
vhdl/Atmel/layout.bin 609 bytes
vhdl/ChipExpress/layout.bin 609 bytes
vhdl/Cypress/layout.bin 609 bytes
vhdl/LatticeCPLD/layout.bin 609 bytes
vhdl/LatticeORCA/layout.bin 609 bytes
vhdl/QuickL/layout.bin 609 bytes
vhdl/Triscend/layout.bin 609 bytes
vhdl/Xilinx/layout.bin 609 bytes
SCH/Xilinx/os.dat 450 bytes
VERILOG/Actel/os.dat 450 bytes
VERILOG/Altera/os.dat 450 bytes
VERILOG/Atmel/os.dat 450 bytes
VERILOG/ChipExpress/os.dat 450 bytes
VERILOG/Cypress/os.dat 450 bytes
VERILOG/LatticeCPLD/os.dat 450 bytes
VERILOG/LatticeORCA/os.dat 450 bytes
VERILOG/QuickL/os.dat 450 bytes
VERILOG/Triscend/os.dat 450 bytes
VERILOG/Xilinx/os.dat 450 bytes
vhdl/Actel/os.dat 450 bytes
vhdl/Altera/os.dat 450 bytes
vhdl/Atmel/os.dat 450 bytes
vhdl/ChipExpress/os.dat 450 bytes
vhdl/Cypress/os.dat 450 bytes
vhdl/LatticeCPLD/os.dat 450 bytes
vhdl/LatticeORCA/os.dat 450 bytes
vhdl/QuickL/os.dat 450 bytes
vhdl/Triscend/os.dat 450 bytes
vhdl/Xilinx/os.dat 450 bytes
os.dat 450 bytes
file_id.diz 432 bytes
ReleaseN.htm 404 bytes
VERILOG/ChipExpress/SETUP.INI 111 bytes
VERILOG/LatticeCPLD/SETUP.INI 111 bytes
VERILOG/LatticeORCA/SETUP.INI 111 bytes
VERILOG/QuickL/SETUP.INI 109 bytes
vhdl/ChipExpress/SETUP.INI 108 bytes
vhdl/LatticeCPLD/SETUP.INI 108 bytes
vhdl/LatticeORCA/SETUP.INI 108 bytes
SCH/Xilinx/SETUP.INI 107 bytes
VERILOG/Triscend/SETUP.INI 107 bytes
VERILOG/Cypress/SETUP.INI 106 bytes
vhdl/QuickL/SETUP.INI 106 bytes
VERILOG/Altera/SETUP.INI 105 bytes
VERILOG/Xilinx/SETUP.INI 105 bytes
VERILOG/Actel/SETUP.INI 104 bytes
VERILOG/Atmel/SETUP.INI 104 bytes
vhdl/Triscend/SETUP.INI 104 bytes
vhdl/Cypress/SETUP.INI 103 bytes
vhdl/Altera/SETUP.INI 102 bytes
vhdl/Xilinx/SETUP.INI 102 bytes
vhdl/Actel/SETUP.INI 101 bytes
vhdl/Atmel/SETUP.INI 101 bytes
SETUP.INI 100 bytes
DATA.TAG 97 bytes
A35reg.htm 90 bytes
SCH/Xilinx/DATA.TAG 87 bytes
VERILOG/Actel/DATA.TAG 87 bytes
VERILOG/Altera/DATA.TAG 87 bytes
VERILOG/Atmel/DATA.TAG 87 bytes
VERILOG/ChipExpress/DATA.TAG 87 bytes
VERILOG/Cypress/DATA.TAG 87 bytes
VERILOG/LatticeCPLD/DATA.TAG 87 bytes
VERILOG/LatticeORCA/DATA.TAG 87 bytes
VERILOG/QuickL/DATA.TAG 87 bytes
VERILOG/Triscend/DATA.TAG 87 bytes
VERILOG/Xilinx/DATA.TAG 87 bytes
vhdl/Actel/DATA.TAG 87 bytes
vhdl/Altera/DATA.TAG 87 bytes
vhdl/Atmel/DATA.TAG 87 bytes
vhdl/ChipExpress/DATA.TAG 87 bytes
vhdl/Cypress/DATA.TAG 87 bytes
vhdl/LatticeCPLD/DATA.TAG 87 bytes
vhdl/LatticeORCA/DATA.TAG 87 bytes
vhdl/QuickL/DATA.TAG 87 bytes
vhdl/Triscend/DATA.TAG 87 bytes
vhdl/Xilinx/DATA.TAG 87 bytes
SCH/Xilinx/setup.lid 49 bytes
VERILOG/Actel/setup.lid 49 bytes
VERILOG/Altera/setup.lid 49 bytes
VERILOG/Atmel/setup.lid 49 bytes
VERILOG/ChipExpress/setup.lid 49 bytes
VERILOG/Cypress/setup.lid 49 bytes
VERILOG/LatticeCPLD/setup.lid 49 bytes
VERILOG/LatticeORCA/setup.lid 49 bytes
VERILOG/QuickL/setup.lid 49 bytes
VERILOG/Triscend/setup.lid 49 bytes
VERILOG/Xilinx/setup.lid 49 bytes
vhdl/Actel/setup.lid 49 bytes
vhdl/Altera/setup.lid 49 bytes
vhdl/Atmel/setup.lid 49 bytes
vhdl/ChipExpress/setup.lid 49 bytes
vhdl/Cypress/setup.lid 49 bytes
vhdl/LatticeCPLD/setup.lid 49 bytes
vhdl/LatticeORCA/setup.lid 49 bytes
vhdl/QuickL/setup.lid 49 bytes
vhdl/Triscend/setup.lid 49 bytes
vhdl/Xilinx/setup.lid 49 bytes
setup.lid 49 bytes
vssver.scc 48 bytes
SCH/Xilinx/build.nfo 17 bytes
VERILOG/Actel/build.nfo 17 bytes
VERILOG/Altera/build.nfo 17 bytes
VERILOG/Atmel/build.nfo 17 bytes
VERILOG/ChipExpress/build.nfo 17 bytes
VERILOG/Cypress/build.nfo 17 bytes
VERILOG/LatticeCPLD/build.nfo 17 bytes
VERILOG/LatticeORCA/build.nfo 17 bytes
VERILOG/QuickL/build.nfo 17 bytes
VERILOG/Triscend/build.nfo 17 bytes
VERILOG/Xilinx/build.nfo 17 bytes
vhdl/Actel/build.nfo 17 bytes
vhdl/Altera/build.nfo 17 bytes
vhdl/Atmel/build.nfo 17 bytes
vhdl/ChipExpress/build.nfo 17 bytes
vhdl/Cypress/build.nfo 17 bytes
vhdl/LatticeCPLD/build.nfo 17 bytes
vhdl/LatticeORCA/build.nfo 17 bytes
vhdl/QuickL/build.nfo 17 bytes
vhdl/Triscend/build.nfo 17 bytes
vhdl/Xilinx/build.nfo 17 bytes
build.nfo 17 bytes

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